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STT-MRAM for Mobile System-on-Chip : Status and Outlook

Mercredi 16 octobre 2013 11:00 - Duree : 1 heure
Lieu : Salle de Séminaire de SPINTEC, Bât 1005 au 2ème étage, CEA Grenoble, 17 rue des martyrs

Orateur : Dr. Seung H. KANG (Advanced Memory Technology group at Qualcomm Technologies )

In the past few years, the spintronics IC community has achieved significant discoveries and engineering breakthroughs [1]. Most recognized is the emergence of STT-MRAM. Key findings and advances have triggered industry-wide R&D efforts in pursuit of an alternative memory in lieu of conventional memories that are not only facing acute tradeoffs in performance and power, but also nearing physical scaling limits. In parallel, various forms of MTJ-based logic devices and circuits have been demonstrated, opening a possible path for spintronic ICs to expand beyond STT-MRAM. Advanced mobile computing and connectivity systems are becoming ever sophisticated in their architectures for which energy efficiency is a critical figure of merit. STT-MRAM offers intrinsically compelling attributes which can bring disruptive memory innovations for advanced system-on-chip (SOC). STT-MRAM can be designed and integrated in a fully logic-compatible way both in supply voltage and in process. Furthermore, embedded STT-MRAM can be offered in a variety of macros whose attributes are tailored for application-specific SOC. For the near term, STT-MRAM is positioned as an embedded nonvolatile memory (NVM) to serve battery-powered mobile connectivity systems. This type of STT-MRAM can provide a memory subsystem not only by storing codes, but also by storing and executing fast data. This simplifies the conventional memory subsystem and also extends battery life. Furthermore, its logic-friendly design and process compatibility can realize such benefits at advanced CMOS nodes for which there is no conventional NVM alternative. A potentially more disruptive opportunity is found in high-performance STT-MRAM which can serve as an alternative to 6T-SRAM or embedded DRAM in emerging CMOS nodes. One example is Level-3 cache for mobile processors. Despite the fact that STT-MRAM is slower than 6T-SRAM as a device, the memory subsystem can be architected in a way that the performance can be comparable or possibly better at a system level. In addition, there is a significant range of SRAM for which its leakage power and cost (chip area) are critical drawbacks. Moving beyond R&D, significant efforts are needed in the following areas for this technology to become mainstream in the semiconductor ecosystem : (1) high-volume manufacturing infrastructure, (2) reliability, and (3) economics. In addition, successful products are likely to desire innovative system architectures to harvest the merits of STT-MRAM, rather than to adopt it as a direct replacement of conventional memory.

[1] S.H. Kang and K. Lee, “Emerging Materials and Devices in Spintronic Integrated Circuits for Energy-Smart Mobile Computing and Connectivity”, Acta Materialia (The Diamond Jubilee Issue), Vol.61, p.952-973 (2013)

BIO : Seung Kang received his Ph.D. in Materials Science and Engineering from the University of California, Berkeley, in 1996, following his B.S. (graduated top of class) and M.S. from Seoul National University, Korea. He then worked as Materials Scientist/Engineer at Lawrence Berkeley National Laboratory in the fields of SQUID sensors and VLSI interconnects. In 1998, he joined Lucent Technologies Bell Laboratories’ VLSI R&D organization as Member of Technical Staff and later was elevated to Distinguished Member of Technical Staff. At the company he led a variety of advanced materials and technology reliability projects. In 2006, he joined Qualcomm, and currently as Principal Manager is leading an emerging memory technology group under the Advanced Technology Initiatives. Dr. Kang has co-organized and co-chaired 10 international conferences and edited or co-edited 6 special journal issues. He has served at numerous technical committees, including IEDM, ISQED, VLSI-TSA, and TMS Nanomaterials Committee and Thin Films and Interfaces Committee. He has published about 50 papers and holds over 60 issued or pending US Patents. He is currently the Chair of TMS Nanomaterials Committee, a Council Member of TMS Electronic, Magnetic & Photonic Materials Division, and an IEEE Senior Member.

Contact :olivier.boulle@cea.fr

Discipline évènement : (Physique)
Entité organisatrice : (INAC/SPINTEC)
Nature évènement : (Séminaire)
Evènement répétitif : (Séminaire nanomagnétisme et électronique de spin)
Site de l'évènement : Site CEA avec accès badge

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