« juin 2018 »
L M M J V S D
28 29 30 31 1 2 3
4 5 6 7 8 9 10
11 12 13 14 15 16 17
18 19 20 21 22 23 24
25 26 27 28 29 30 1
 
Tous les évènements de Physique à venir

Tous les évènements de Biologie / Chimie à venir

Tous les évènements à venir

Les évènements relevant de la Physique et de la Biologie / Chimie sont représentés en turquoise

Future of Logic Nano CMOS Technology

Mardi 14 octobre 2014 13:00 - Duree : 1 heure
Lieu : Salle M253, PHELMA, Bât. INP, MINATEC

Orateur : Hiroshi IWAI (Tokyo Institute of Technology, Japan)

Although Si MOSFETs have dominated the integrated circuit applications over the past four decades, it is anticipated that the development of CMOS would reach MOSFET downsizing li mits sometime after the next decade. However, there are no promising candidates which can replace CMOS with better performance for high-density integration with low cost for the moment. Thus, maybe, we have to stick to the CMOS devices until its end. In order to pursue the downsizing of CMOS for another decade, the development of new technologies is becoming extremely important. Not all the companies can necessarily develop the most advanced technology timely and the competition between the leading semiconductor manufacturing companies becomes very severe for their survive. The current status of the frontend of the technologies is as follows : Because of the difficulty in the lithography and also in the Ion/Ioff ratio control, the rate of the shrinkage for the line pitch and gate length becomes significantly less aggressive so that we will face the downsizing limit later than expected before. New device structures such as multi-gate (FinFET, Tri-gate, and Si-nanowire MOSFETs) and FD (Fully Depleted) SOI are replacing conventional planar MOSFETs. Continuous innovation of High-k/metal gate technologies has enabled EOT scaling down to 0.9 – 0.8 nm in production, however, introduction of new materials are desirable for further EOT scaling. In order to decrease the gate length of MOSFETs down to deep sub-10 nm, we have to solve very difficult problems, significant increase in subthreshold current, significant decrease in conduction for small fin width multigate, ultra-thin Si SOI and small EOT high-k MOSFETs, significant increase of gate leakage current and reliability degradation for small EOT MOSFETs, and through-put decrease for very fine lithography. At this moment, we do not know the solutions for those problems, although there are many good challenges in emerging technologies. In this seminar, past, now, and future of logic MOS LSI technologies are explained.

http://imep-lahc.grenoble-inp.fr/events/seminar-by-prof-hiroshi-iwai-tuesday-october-14-2014-639230.kjsp?RH=IMEP_FR

Contact : bauza@minatec.grenoble-inp.fr

Discipline évènement : (Physique)
Entité organisatrice : (IMEP/LAHC)
Nature évènement : (Séminaire)
Evènement répétitif : (Séminaire IMEP-LAHC)
Site de l'évènement : Site Minatec

Prévenir un ami par email

Télécharger dans mon agenda

Cafés sciences de Grenoble | UdPPC de Grenoble | Sauvons Le Climat | Cafe des sciences de Vizille
Accueil du site | Secretariat | Espace privé | Suivre la vie du site RSS 2.0 : Tous les evenements Suivre la vie du site RSS 2.0 : Evenements de Physique Suivre la vie du site RSS 2.0 : Evenements de Biologie & Chimie