Macroscopic and stochastic aspects of negative bias temperature instability in CMOS devices and circuits

Orateur : Souvik MAHAPATRA (Dept. of Electrical Engineering, Indian Institute of Technology, Bombay, India - IEEE-EDS Distinguished Lecturer)

Negative Bias Temperature Instability (NBTI) is a crucial reliability concern for modern day state-of-the-art CMOS tec hnologies. NBTI results in shift in MOSFET parameters, such as threshold voltage, drain current, etc., over time, and therefore causes long-time failure of CMOS integrated circuits. It is very important to understand the fundamental physical mechanism responsible for NBTI and develop suitable models to predict device and resultant circuit degradation at end product life. In this talk, the underlying physical processes responsible for NBTI in High-K Metal Gate (HKMG) MOSFETs will be briefly reviewed. Defect generation in MOSFET gate oxide will be explained from both macroscopic and stochastic viewpoints, which will be respectively useful to explain NBTI degradation in large and small area devices. This novel simulation framework can explain DC and AC NBTI degradation under various operating conditions such as different operating voltage, temperature, frequency and duty cycle in large area devices, as well as NBTI variability in small area devices. Furthermore, a compact model will be developed to simulate NBTI induced circuit degradation using SPICE simulation, and specific example of variable NBTI impact on SRAM performance parameters, such as read and hold static noise margin and write access time will be discussed.

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