Material developments and nanosecond-scale switching process in perpendicularly magnetized STT-MRAM cells

Orateur : Thibaut DEVOLDER (Centre de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Sud, Université Paris-Saclay, C2N-Orsay, 91405 Orsay cedex, France)

We investigate the Gilbert damping and the magnetization switching of perpendicularly magnetized FeCoB-based free layers embedded in magnetic tunnel junctions adequate for spin-torque operated magnetic memories. We first study the influence of the boron content in MgO / FeCoB /Ta systems alloys on their Gilbert damping parameter after crystallization annealing. Increasing the boron content from 20 to 30% increases the crystallization temperature, thereby postponing the onset of elemental diffusion within the free layer. This reduction of the interdiffusion of the Ta atoms helps maintaining the Gilbert damping at a low level of 0.009 without any penalty on the anisotropy and the magneto-transport properties up to the 400°C annealing required in CMOS back-end of line processing. In addition, we show that dual MgO free layers of composition MgO/FeCoB/Ta/FeCoB/MgO have a substantially lower damping than their MgO/FeCoB/Ta counterparts, reaching damping parameters as low as 0.0039 for a 3 Å thick Tantalum spacer. This confirms that the dominant channel of damping is the presence of Ta impurities within the FeCoB alloy. On optimized tunnel junctions, we then study the duration of the switching events induced by spin-transfer-torque. We focus on the sub-threshold thermally activated switching in optimal applied field conditions. From the electrical signatures of the switching, we infer that once the nucleation has occurred, the reversal proceeds by a domain wall sweeping though the device at a few 10 m/s. The smaller the device, the faster its switching. We present an analytical model to account for our findings. The domain wall velocity is predicted to scale linearly with the current for devices much larger than the wall width. The wall velocity depends on the Bloch domain wall width, such that the devices with the lowest exchange stiffness will be the ones that host the domain walls with the slowest mobilities.

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