SOT-MRAM : from fundamentals to large scale technology integration

Orateur : Kevin GARELLO (Imec, Belgium)

Microelectronics industry is facing major challenges related to the volatility of CMOS cache memory elements (usually SRAM and eDRAM). Due to decreasing de vices size, leakage current in standby mode are now dominating the power dissipation of CMOS circuits. Furthermore, the increased density and reduction in die area lead to heat dissipation and reliability issues. Magnetic RAM (MRAMs) and Spin-Transfer-Torque MRAM (STT-MRAM[1]) are among most credible non-volatile memories candidates that are scalable, low power and with relatively low access times, as well as a compatibility with scaled CMOS processes and voltages. In fact, past years have seen major foundries and tool suppliers investing significant R&D resources into embedded STT-MRAM. They recently started prototyping demonstrators, progressively maturing for mass production for embedded memories.

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